FIG. 1 illustrates a typical ROM device in which ATD technology is implemented. As shown in this figure, input buffers 12, 14, 16 and 18 receive a chip enable signal, row address signals, column address signals and an output enable signal which are applied externally, and output internal signals such as a chip enable signal CEPi, a row address signal RAPi, a column address signal CAPi and an output enable signal OEi. These signals RAPi and CAPi from the row and column address buffers 14 and 16 are applied to the row predecoder 26 and column predecoder 28, respectively. The predecoders 26 and 28 are provided to select specific memory cells of the cell array 10 in response to the signals RAPi and CAPi. The signals CEPi, RAPi and CAPi from the buffers 12, 14 and 16 are applied to the short pulse generation circuits 34,36 and 38 of the ATM circuit 30. The short pulse generation circuit 34 generates a short pulse signal every time transition of the chip enable signal CEPi occurs. Each of the other circuits 36 and 38 also generates a short pulse signal every time transition of at least one input address occurs. All of the short pulse signals generated thus are applied to the summator 40, which generates a pulse signal SMO having a preset width by adding widths of the applied short pulse signals. The read control circuit 42 generates a precharge control signal PRE and a sense amp control signal SACS in response to the pulse signal SMO provided from the summator 40. Then, the precharging operation of the bit lines is carried out while the precharge control signal PRE is maintained at a predetermined voltage level.
Sense amplifier circuit 22 amplifies data signals which are stored in memory cells selected by the predecoders 26 and 28, and provides them to the data latch circuit 24. Output signals of the data latch circuit 24 are provided to external circuits (not shown) via the data output buffer 32 in response to the output enable signal OEi.
As shown in FIG. 2 which shows a prior art NOR type mask ROM with hierarchical bit line architecture, each cell array block of the mask ROM is formed in a such manner that bit lines are arranged in hierarchical form. As an example, bit lines are constituted with extended main bit lines MBL1, MBL2, . . . , and sub-bit lines SBL1, SBL2, . . . along corresponding columns defined on a substrate. Each main bit line is a metal bit line which is composed of aluminum, and each sum-bit line is a diffusion bit line which is composed of a diffusion layer. Two sub-bit lines are arranged corresponding to one main bit line. In each cell array block, the sub-bit lines are classified into two groups. Of the two groups, one group is formed by odd-numbered sub-bit lines SBL1, SBL3, . . . , etc. and the other group is formed by even-numbered sub-bit lines SBL2, SBL4, . . . etc. Two even-numbered sub-bit lines correspond to one ground line GL. Two odd-numbered and two even-numbered sub-bit lines are interdigitated to one another.
In each cell array block of FIG. 2, the memory cells Mmn (where m=1, 2, . . . , I; and n=1, 2, . . . , j) composed of MOSFETs are connected in parallel with a plurality of sub-bit lines SBL1, SBL2, . . . , etc. which are intersected with word lines WL1.about.WLi. As an example, each memory cell Mmn is arranged in each cell region which is defined by intersecting each pair of sub-bit lines SBL1 and SBL2, SBL3 and SBL4, . . . etc. extending in column direction with the word lines WL1.about.WLi extending in row direction. Gates of the memory cells which are arranged in the row direction are connected to corresponding word lines. As well-known in this art, each memory cell composed of MOSFETs is programmed to either an on-cell state or an off-cell state. Herein, the on-cell state means that the memory cell is at a low threshold voltage (e.g., 0.5 V), and the off-cell state means that the memory cell is at a high threshold voltage (e.g., 5 V).
Memory cells M1k, M2k, . . . , Mik (where k is an integer which is 1 or more) in respective columns between two adjacent sub-bit lines SBL1 and SBL2, SBL2 and SBL3, SBL3 and SBL4, . . . , etc. constitute a single string or a bank. Between two adjacent odd-numbered sub-bit lines SBL2k-1 and SBL2k+1, for example, SBL1 and SBL3, SBL3 and SBL5, . . . , etc. and between two adjacent even-numbered sub-bit lines SBL2k and SBL2k+2, for example, SBL2 and SBL4, SBL4 and SBL6, . . . , etc. two cell strings are assigned. Sources of memory cells in two adjacent strings are commonly connected to corresponding even-numbered sub-bit lines SBL2k, and drains thereof are connected to two odd-numbered sub-bit lines SBL2k-1 and SBL2k+1 at both sides of each strings, respectively. For example, the sources of the cells M13 and M14 are commonly connected to the sub-bit line SBL4, and the drains thereof are connected to the sub-bit lines SBL3 and SBL5, respectively. Odd-numbered sub-bit lines SBL1, SBL3, . . . , etc. are electrically connected to the main bit lines MBL1, MBL2, . . . , etc. via a first string selection circuit which is constituted with string selecting nMOSFETs STI, ST2, . . . , etc., respectively. Similarly, even-numbered sub-bit lines SBL2, SBL4, . . . , etc. are electrically connected to the ground lines GL1, GL2, . . . , etc. via a second string selection circuit which is constituted with ground selecting MOSFETs GT1, GT2, . . . , etc., respectively. The main bit lines MBL1, MBL2, . . . , etc. are electrically connected to the sense amplifiers SA1, SA2, . . . , etc. via a group of first column selecting MOSFETs GBT1, GBT2, . . . , etc., respectively, and the ground lines GL1, GL2, . . . , etc. are connected to the ground Vss via a group of second column selecting MOSFETs GBT1, GBT, . . . , etc.
The typical ROM device of FIG. 1 can be reduced in parasitic capacitance of the bit lines, as compared with the prior art NOR type ROM device of FIG. 2. Particularly, when the bit lines are composed of diffusion layers, a wiring resistance thereof is considerably reduced.
However, during the bit line precharge operation for reading data stored in memory cells, the bit line precharge state may be greatly varied in accordance with programing states of both the memory cell to be selected and the adjacent memory cell thereof. As an example, in case memory cells adjacent to the memory cell to be selected are programmed as off-cells, the main bit line related to the selected memory cell is normally precharged, so that the cell reading operation can be normally carried out. If all the memory cells M11.about.M14 of FIG. 2 are programmed as on-cells and the memory cell M15 as off-cell, after the main bit line MBL2 starts to be precharged, the precharge level of the main bit line MBL1 is not maintained to a specific level and is dropt down, by allowing the word line WL1 to be activated and the string selecting MOSFET ST3 to be turned on, between the selection of the memory cell 15 and the data sensing thereof. This is because, when the word line WL1 is activated, all the memory cells M11.about.M14 are turned on and thereby leakage current flows to the sub-bit lines SBL4, SBL3, SBL2 and SBL1, passing through the main bit line MBL2, the sub-bit line SBL5, the cells M14, M13, M12 and M11 sequentially. As a result, the sub-bit lines SBL4, SBL3, SBL2 and SBL1 are functioned as loads of the selected main bit line MBL2. Precharge level drop of the main bit line leads to reduction in data sensing margin, and acts as a factor of limiting high-speed read operation of mask ROM devices. Also, the mask ROM devices having the above described construction is not possible to operate with a low power supply Vcc.